1. Field of the Invention
The invention relates to a signal processing circuit for a charge-coupled device, more particularly to a signal processing circuit which is capable of minimizing the presence of noise at the outputs of the charge-coupled device.
2. Description of the Related Art
Referring to FIG. 1, the output stage of a conventional charge-coupled device (CCD) is shown to comprise a reference signal circuit 1 and a CCD signal circuit 2. The reference signal circuit 1 includes an output control gate 11, a floating diode sense capacitor 12, a reset gate 13, and a reset drain 14. The CCD signal circuit 2 includes a CCD register 21, an output control gate 22, a floating diode sense capacitor 23, a reset gate 24, and a reset drain 25. The reference signal circuit 1 generates an output signal (VIC) which is obtained from the sense capacitor 12 and which serves as a reference voltage level. The CCD signal circuit 2 generates an output signal (VIO) which is taken from the sense capacitor 23 and which contains scanned data signals.
FIG. 2 illustrates a conventional signal processing circuit 3 for the output stage of the conventional charge-coupled device. The signal processing circuit 3 comprises a differential circuit 31, an amplifier 32 and an output buffer 33. The differential circuit 31 receives the outputs signals (VIC, VIO) from the reference signal circuit 1 and the CCD signal circuit 2. The output of the differential circuit 31 is amplified by the amplifier 32 before being provided to the output buffer 33.
FIG. 5A illustrates a sample output signal (Vo) which can be obtained from the signal processing circuit 3. The sample output signal (Vo) is divided into four signal output periods (M0-M3). Each output period is further divided into three sub-periods (tn, to, ts). A reset noise is present during the sub-period (tn) and is induced at the sense capacitors 12, 23 by the clock input (.phi.R) to the reset gates 13, 24 of the reference signal circuit 1 and the CCD signal circuit 2. The differential circuit 31 of the signal processing circuit 3 serves to minimize the effect of the reset noise during the sub-period (tn). The presence of the sub-period (to) permits isolation of the reset noise from the data signal present during the sub-period (ts).
In the sample output signal (Vo) shown in FIG. 5A, noise signals (-N1) and (+N2) can occur during the sub-periods (to, ts) of the periods (M1, M2), thereby affecting the precision of the charge-coupled device. Similarly, the occurrence of a noise signal (+N3) during the sub-period (ts) of the period (M3) also affects the precision of the charge-coupled device.
An improved signal processing circuit 30 has been developed in order to overcome most of the drawbacks of the signal processing circuit 3 shown in FIG. 2. Referring to FIG. 3, the signal processing circuit 30 comprises a differential circuit 31, a MOS amplifier 32, an output buffer 33, a control gate 34 and a delay circuit 35. The differential circuit 31 receives the output signals (VIC, VIO) from the reference signal circuit 1 and the CCD signal circuit 2. A first one of the inputs of the amplifier 32 is connected to the output of the differential circuit 31. A second one of the inputs of the amplifier 32 and the output of the latter are connected to the control gate 34. The delay circuit 35 receives the clock input (.phi.R) to the reset gates 13, 24 of the reference signal circuit 1 and the CCD signal circuit 2 shown in FIG. 1, and controls the control gate 34 to provide a negative feedback input to the amplifier 32 during the sub-periods (tn, to), as shown in FIG. 5C, thereby minimizing the amplification factor of noise signals present during the sub-periods (tn, to). The output of the amplifier 32 is provided to the output buffer 33.
FIG. 5B illustrates a sample output signal (Vo') which can be obtained from the signal processing circuit 30. Note that the effect of the noise signals (-N1, +N2) during the sub-period (ts) of the periods (M1, M2) is minimized. However, the signal processing circuit 30 is unable to reduce the effect of the noise signal (+N3) present during the sub-period (ts) of the period (M3). Furthermore, the switching action of the control gate 34 introduces transient noise into the output signal (Vo') of the signal processing circuit 30. This can affect the quality of the output of the charge-coupled device.